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![sandpile.org](./pics/sandpile.gif)
The world's leading source for technical x86 processor information.
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regs
general purpose registers
rFLAGS
masks | bounds | CET
segment registers
table registers
control registers
debug registers
legacy FP | vector FP
model specific registers
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code
opcode encodings
1 byte opcodes
2 byte opcodes
3 byte opcodes
map 4 opcodes
opcode groups | FPU opcodes
3DNow! | SSE5A | XOP | L1OM
mod R/M byte and SIB byte
16-bit mod R/M byte
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data
binary | ternary
datatypes
stack frames
selectors
descriptors
descriptor tables
task state segments
paging structures
system management mode
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misc
condition codes
exceptions | interrupts
legacy stuff | APIC
Intel VMX | AMD SVM
coherency
execution mode
initial state
canonical addresses
CPUID
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