Rise mP6
| General Details | Name | mP6 | |
| Codename |
6401 (0.25 µm, 2.0x Multiplier) Kirin or 6441 (0.25 µm, 2.0x and 2.5x Multiplier) Lynx or 6510 (0.18 µm) |
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| Family/Generation | 80586, 5th Generation, MMX | ||
| Vendor | Rise | ||
| Manufacturer | TSMC | ||
| First Introduction |
Oct 13, 1998 (PR166, PR233, PR266) May 26, 1999 (0.25 µm PR333 and PR366) May 26, 1999 (0.18 µm PR333 and PR366) |
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| Physical Details | Package Type |
296 Pin BPGA 387 Pin T2BGA (Turbo Thermal BGA) |
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| Package Size |
4.95 cm x 4.95 cm (BPGA) 3.50 cm x 3.50 cm (T2BGA) |
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| Socket or Slot |
Socket 7 (BPGA) Proprietary (T2BGA) |
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| Transistors | 3,600,000 (includes 2x 8 KB L1 Cache) | ||
| Process Technology |
5M, 0.25 µm, CMOS ???, 0.18 µm, CMOS |
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| Die Size |
107 mm² (0.25 µm) ??? mm² (0.18 µm) |
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| Electrical Details | Split Voltage | Yes (determined via Motherboard) | |
| Core Voltage |
2.8 V (0.25 µm) 2.0 V (0.18 µm) |
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| I/O Voltage | 3.3 V | ||
| Typical Power |
166 MHz: 5.28 W (0.25 µm PR166) 190 MHz: 5.96 W (0.25 µm PR233) 200 MHz: 6.28 W (0.25 µm PR266) 237.5 MHz: 7.47 W (0.25 µm PR333) 250 MHz: 7.87 W (0.25 µm PR366) 237.5 MHz: 3.53 W (0.18 µm PR333) 250 MHz: 3.66 W (0.18 µm PR366) |
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| Maximum Power |
166 MHz: 7.28 W (0.25 µm PR166) 190 MHz: 8.11 W (0.25 µm PR233) 200 MHz: 8.54 W (0.25 µm PR266) 237.5 MHz: 10.18 W (0.25 µm PR333) 250 MHz: 10.72 W (0.25 µm PR366) 237.5 MHz: 4.78 W (0.18 µm PR333) 250 MHz: 5.00 W (0.18 µm PR366) |
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| Cooling | Required | ||
| Clock Frequencies | CPU Core Speed |
PR166: 166/83 MHz PR233: 190/95 MHz PR266: 200/100 MHz PR333: 237.5/95 MHz PR366: 250/100 MHz |
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| L1 Cache Speed | 1.0x Core Speed | ||
| L2 Cache Speed | 1.0x External Bus Speed | ||
| External Bus Speed | 60, 66, 75, 83, 95, or 100 MHz | ||
| Core/Bus Ratio | 2.0x, 2.5x, 3.0x, 3.5x | ||
| Miscellaneous | usual Motherboard | Single Processor Socket 7 | |
| usual Chipset | Intel 82430FX, 82430HX, 82430VX, 82430TX, or non-Intel | ||
| Pictures | CPUID=0504h Top (113 KB JPG) and Bottom (120 KB JPG) | ||
| Processor Core | Generic Details | CISC, In-order Execution | |
| Specific Details |
3-Stage Non-interlocking Code Fetch Pipeline 2-Stage Non-interlocking Data Fetch Pipeline |
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| Registers | 32 Bit Integer, 80 Bit FP, 64 Bit MM | ||
| Pipeline Depth | 8 Stages | ||
| Instruction Decoder | up to 3x IA-32/Cycle | ||
| Execution Units |
3x ALU (1x Shift/MUL/DIV, 1x three-input, 1x MOV/Jcc) 7x MMX (ADD, MUL, CMP, Pack, Shift, 2x Unpack/Boolean) 1x Pipelined FPU |
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| Execution Speed | up to 3x IA-32/Cycle, up to 3x MMX/Cycle | ||
| Processor Buses | Address Bus Width | 32 Bit | |
| Data Bus Width | 64 Bit | ||
| Physical Memory | 2^32 Bit = 4 GB | ||
| Virtual Memory | 2^32 Bit = 4 GB | ||
| Logical Memory | (8,190 + 8,192) x 4 GB = 65,528 GB (~64 TB) | ||
| Multiprocessing | N/A | ||
| Power Management |
HLT, STPCLK, SMI/SMM Facility Gating, Necessary Switching Only, Required Selection Only |
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| Processor Caches | Level 0 | N/A | |
| Level 1 | Code | 8 KB, 2-Way | |
| Data | 8 KB, 2-Way, Dual-ported, Triple-ported Tags | ||
| Level 2 | Unified | External, depends on Motherboard | |
| Processor Buffers | Read Buffer | ??? | |
| Write Buffer | ??? | ||
| Prefetch Queue | 56 Byte Instruction Buffer | ||
| Branch Prediction | Static | Yes | |
| Dynamic |
512 Entries, 2-Way up to 4 Instruction Streams ahead |
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| RSB | 8 Entries | ||
| TLB | Code | ??? | |
| Data | ??? | ||
| Instruction Set | Regular | IA-32 | |
| Floating Point | Integrated | ||
| Multi Media | MMX | ||
| Processor Modes | Real, Protected, Virtual, Paging, SMM | ||
