x86 architecture CET
shadow stack registers |
name |
6 3 |
|
3 2 |
3 1 |
|
1 2 |
1 1 |
1 0 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
SSP |
SSP |
PL0_SSP MSR |
CPL0 SSP |
PL1_SSP MSR |
CPL1 SSP |
PL2_SSP MSR |
CPL2 SSP |
PL3_SSP MSR |
CPL3 SSP |
res. |
IST_SSP MSR |
interrupt SSP table base |
S_CET MSR |
ENDBRANCH legacy bitmap base |
T R K |
S U P |
reserved |
W SS HT K |
SS HT K |
L E G IW |
E N D BR |
U_CET MSR |
ENDBRANCH legacy bitmap base |
T R K |
S U P |
reserved |
W SS HT K |
SS HT K |
L E G IW |
E N D BR |
|