x86 architecture L1OM transform modifiers
L1OM.sss |
|
L1OM.sss and disp8*N |
000b |
001b |
010b |
011b |
100b |
101b |
110b |
111b |
|
S*(reg) |
{dcba} |
{cdab} |
{badc} |
{aaaa} |
{bbbb} |
{cccc} |
{dddd} |
{dacb} |
|
Si32(mem) |
{16to16} [/1] |
{1to16} [/16] |
{4to16} [/4] |
reserved |
{uint8} [/4] |
{sint8} [/4] |
{uint16} [/2] |
{sint16} [/2] |
Sf32(mem) |
{16to16} [/1] |
{1to16} [/16] |
{4to16} [/4] |
reserved |
{uint8} [/4] |
{unorm8} [/4] |
{float16} [/2] |
{sint16} [/2] |
|
Si64(mem) |
{8to8} [/1] |
{1to8} [/8] |
{4to8} [/2] |
reserved |
reserved |
reserved |
reserved |
reserved |
Sf64(mem) |
{8to8} [/1] |
{1to8} [/8] |
{4to8} [/2] |
reserved |
reserved |
reserved |
reserved |
reserved |
|
*ld32(mem) |
{16to16} [/1] |
{1to16} [/16] |
{4to16} [/4] |
reserved |
reserved |
reserved |
reserved |
reserved |
*ld64(mem) |
{8to8} [/1] |
{1to8} [/8] |
{4to8} [/2] |
reserved |
reserved |
reserved |
reserved |
reserved |
|
*st32(reg) |
{all} [/1] |
{a} [/16] |
{dcba} [/4] |
reserved |
reserved |
reserved |
reserved |
reserved |
*st64(reg) |
{all} [/1] |
{a} [/8] |
{dcba} [/2] |
reserved |
reserved |
reserved |
reserved |
reserved |
L1OM condition codes |
|
L1OM.opc.2 + L1OM.R'R |
000b |
001b |
010b |
011b |
100b |
101b |
110b |
111b |
|
VCMPcc[PS|PD] |
{eq} |
{lt} |
{le} |
{unord} |
{neq} |
{nlt} |
{nle} |
{ord} |
VCMPcc[PI|PU] |
{eq} |
{lt} |
{le} |
reserved |
{neq} |
{nlt} |
{nle} |
reserved |
L1OM.fld |
|
L1OM.sss used as fld |
000b |
001b |
010b |
011b |
100b |
101b |
110b |
111b |
|
VSTOREBMSKD |
{00FFFFFF} |
{000000FF} |
{FFFFFF00} |
{FF000000} |
reserved |
reserved |
reserved |
reserved |
VCMPBMSKccPU |
{00FFFFFF} |
{000000FF} |
{FFFFFF00} |
{FF000000} |
reserved |
reserved |
reserved |
reserved |
L1OM.ccccc |
|
L1OM.ccccc and disp8*N |
U*32 |
U*64 |
D*32 |
D*64 |
RC (??xxxb) |
ExpAdj (xx???b) |
field (xx0??b) |
low / high (xx00?b) |
|
00000b |
{none} [/1] |
{none} [/1] |
{none} [/1] |
{none} [/1] |
{rn} |
{0b} |
{unorm10A} {float11A} |
{low} |
00001b |
{float16} [/2] |
reserved |
{float16} [/2] |
reserved |
{4b} |
{unorm10B} {float11B} |
{high} |
00010b |
reserved |
reserved |
{float16rz} [/2] |
reserved |
{5b} |
{unorm10C} {float10C} |
|
00011b |
{srgb8} [/4] |
reserved |
reserved |
reserved |
{8b} |
{unorm2D} {none} |
00100b |
{uint8} [/4] |
reserved |
{uint8} [/4] |
reserved |
{16b} |
|
00101b |
{sint8} [/4] |
reserved |
{sint8} [/4] |
reserved |
{24b} |
00110b |
{unorm8} [/4] |
reserved |
{unorm8} [/4] |
reserved |
{31b} |
00111b |
{snorm8} [/4] |
reserved |
{snorm8} [/4] |
reserved |
{32b} |
|
01000b |
{uint16} [/2] |
reserved |
{uint16} [/2] |
reserved |
{rd} |
|
01001b |
{sint16} [/2] |
reserved |
{sint16} [/2] |
reserved |
01010b |
{unorm16} [/2] |
reserved |
{unorm16} [/2] |
reserved |
01011b |
{snorm16} [/2] |
reserved |
{snorm16} [/2] |
reserved |
01100b |
{uint8i} [/4] |
reserved |
{uint8i} [/4] |
reserved |
01101b |
{sint8i} [/4] |
reserved |
{sint8i} [/4] |
reserved |
01110b |
{uint16i} [/2] |
reserved |
{uint16i} [/2] |
reserved |
01111b |
{sint16i} [/2] |
reserved |
{sint16i} [/2] |
reserved |
|
10000b |
{unorm10A} [/1] |
reserved |
reserved |
reserved |
{ru} |
|
10001b |
{unorm10B} [/1] |
reserved |
reserved |
reserved |
10010b |
{unorm10C} [/1] |
reserved |
reserved |
reserved |
10011b |
{unorm2D} [/1] |
reserved |
reserved |
reserved |
10100b |
{float11A} [/1] |
reserved |
reserved |
reserved |
10101b |
{float11B} [/1] |
reserved |
reserved |
reserved |
10110b |
{float10C} [/1] |
reserved |
reserved |
reserved |
10111b |
reserved |
reserved |
reserved |
reserved |
|
11000b |
reserved |
reserved |
reserved |
reserved |
{rz} |
|
11001b |
reserved |
reserved |
reserved |
reserved |
11010b |
reserved |
reserved |
reserved |
reserved |
11011b |
reserved |
reserved |
reserved |
reserved |
11100b |
reserved |
reserved |
reserved |
reserved |
11101b |
reserved |
reserved |
reserved |
reserved |
11110b |
reserved |
reserved |
reserved |
reserved |
11111b |
reserved |
reserved |
reserved |
reserved |
© 1996-2024 by Christian Ludloff. All rights reserved. Use at your own risk.
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