x86 architecture
local APIC




 
Advanced Programmable Interrupt Controller
 
register 6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
legacy I/O reg select reg
reserved
 
MMIO offset 000h (n/a)
MSR 0000_0800h (n/a)
reserved
legacy I/O window reg
reserved
 
MMIO offset 010h (n/a)
MSR 0000_0801h (n/a)
reserved
 
ID
 
MMIO offset 020h (RW)
MSR 0000_0802h (RO)
AMD Ext. ID Intel P5       reserved   
APIC ID (classic) – Intel P6      
APIC ID (x2 APIC)
 
VER
 
MMIO offset 030h (RO)
MSR 0000_0803h (RO)
A
M
D
Ext
AVL
reserved EOI
Brd
Cst
Spr
AVL
max LVT entry (n-1) reserved version (0xh vs 10-15h)
 
reserved
 
MMIO offset 040h (n/a)
MSR 0000_0804h (n/a)
reserved
 
reserved
 
MMIO offset 050h (n/a)
MSR 0000_0805h (n/a)
reserved
 
reserved
 
MMIO offset 060h (n/a)
MSR 0000_0806h (n/a)
reserved
 
reserved
 
MMIO offset 070h (n/a)
MSR 0000_0807h (n/a)
reserved
 
TPR
 
MMIO offset 080h (RW)
MSR 0000_0808h (RW)
Although the APIC operates instantaneously, it takes on the order of ~(core frequency / APIC frequency) core clocks for
traffic to travel between the core and the APIC. As a result, when opening and closing an interrupt window for the APIC,
software must ensure a window sufficient for interrupt recognition, e.g. by issuing lower(TPR) + read(TPR) + raise(TPR).
task
priority
class
task
priority
sub-class
P5/P6 only, and AMD
APR
 
MMIO offset 090h (RO)
MSR 0000_0809h (RO)
reserved arbitration
priority
class
arbitration
priority
sub-class
P5+
PPR
 
MMIO offset 0A0h (RO)
MSR 0000_080Ah (RO)
reserved processor
priority
class
processor
priority
sub-class
 
EOI
 
MMIO offset 0B0h (WO)
MSR 0000_080Bh (WOZ)
reserved
DX/P5/P6 only, and AMD
RRR
 
MMIO offset 0C0h (RO)
MSR 0000_080Ch (n/a)
remote read data
 
LDR
 
MMIO offset 0D0h (RW)
MSR 0000_080Dh (RO)
logical APIC ID
(classic)
reserved
logical APIC ID
(x2 APIC)
 
DFR
 
MMIO offset 0E0h (RW)
MSR 0000_080Eh (n/a)
0000b=cluster
1111b=flat
reserved (all 1s)
 
SVR
 
MMIO offset 0F0h (RW)
MSR 0000_080Fh (RW)
reserved EOI
Brd
Cst
Spr
EN
res. Foc
Prc
Chk
DIS
A
PIC
SW
EN
vector
 
ISR
 
MMIO offset 100h (RO)
MSR 0000_0810h (RO)
 
...
 
MMIO offset 170h (RO)
MSR 0000_0817h (RO)
... 1
6
 
reserved
 
2
5
5
...
 
TMR
 
MMIO offset 180h (RO)
MSR 0000_0818h (RO)
 
...
 
MMIO offset 1F0h (RO)
MSR 0000_081Fh (RO)
... 1
6
 
reserved
 
2
5
5
...
 
IRR
 
MMIO offset 200h (RO)
MSR 0000_0820h (RO)
 
...
 
MMIO offset 270h (RO)
MSR 0000_0827h (RO)
... 1
6
 
reserved
 
2
5
5
...
P5+
ESR
 
MMIO offset 280h (RW)
MSR 0000_0828h (RWZ)
ESR is accompanied by an internal TEMP_ESR. A write to ESR copies TEMP_ESR to ESR, and it clears TEMP_ESR.

Any error condition(s) will set the corresponding TEMP_ESR bit(s). Whether an error interupt is (if LVT_ERROR.MASK
permits it) delivered if any "fresh" bit(s) did arrive, or only if TEMP_ESR was all clear before, is implementation-specific.
!P5
Illeg
Reg
Adr
 
Rcv
Illeg
Vec
Snd
Illeg
Vec
Pxx
Red
irec
tabl
IPI
P5/6
Rcv
Acc
ept
Err
P5/6
Snd
Acc
ept
Err
P5/6
Rcv
Chk
sum
Err
P5/6
Snd
Chk
sum
Err
 
reserved
 
MMIO offset 290h (n/a)
MSR 0000_0829h (n/a)
 
...
 
MMIO offset 2E0h (n/a)
MSR 0000_082Eh (n/a)
reserved
NHM+
LVT_CMCI
 
MMIO offset 2F0h (RW)
MSR 0000_082Fh (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

000 = fixed
010 = SMI
100 = NMI
vector
 
ICR
 
MMIO offset 300h (RW)
MMIO offset 310h (RW)
 
MSR 0000_0830h (RW)
 
(only one 64-bit MSR!)
(no MSR 0000_0831h)
destination
(classic)
reserved
destination
(x2 APIC)
                reserved DEST S

0=D 1=S
2=All + S
3=All – S
RR Stat

0|1|2|3 =
inv | pen
| ok | res
TM

edg
or
levl
Lev

de-
or
ass
r. DS

idle
or
pen
Dst

phy
or
log
DEST MODE

0=fix 1=lp 2=S
3=rr 4=N 5=IN
6=SIPI 7=ExtI
vector
82489DX+
LVT_TIMER
 
MMIO offset 320h (RW)
MSR 0000_0832h (RW)
                reserved leg
tmr
bas
sel
MODE

00=once
01=perio
10=TSC-
M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

000 = fixed
 
 
vector
P4+
LVT_THERMAL
 
MMIO offset 330h (RW)
MSR 0000_0833h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

000 = fixed
010 = SMI
100 = NMI
vector
P6+
LVT_PMC
 
MMIO offset 340h (RW)
MSR 0000_0834h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

000 = fixed
010 = SMI
100 = NMI
vector
82489DX+
LVT_LINT0
 
MMIO offset 350h (RW)
MSR 0000_0835h (RW)
reserved M
A
S
K
TM

edg
or
levl
Rm
 
I
R
R
Pol

std
or
inv
DS

idle
or
pen
r. DEST MODE

000 = fixed
2=SMI 5=INIT
4=NMI 7=ExtI
vector
82489DX+
LVT_LINT1
 
MMIO offset 360h (RW)
MSR 0000_0836h (RW)
reserved M
A
S
K
TM

edg
or
levl
Rm
 
I
R
R
Pol

std
or
inv
DS

idle
or
pen
r. DEST MODE

000 = fixed
2=SMI 5=INIT
4=NMI 7=ExtI
vector
P5+
LVT_ERROR
 
MMIO offset 370h (RW)
MSR 0000_0837h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

000 = fixed
 
 
vector
 
TIMER_ICR
 
MMIO offset 380h (RW)
MSR 0000_0838h (RW)
initial counter value
 
TIMER_CCR
 
MMIO offset 390h (RO)
MSR 0000_0839h (RO)
current counter value
 
reserved
 
MMIO offset 3A0h (n/a)
MSR 0000_083Ah (n/a)
 
...
 
MMIO offset 3D0h (n/a)
MSR 0000_083Dh (n/a)
reserved
 
TIMER_DCR
 
MMIO offset 3E0h (RW)
MSR 0000_083Eh (RW)
reserved see
bits
1:0
leg
div
clk
sel
111 = /1
 
n=0...6
= /2n+1
x2 APIC
SELF_IPI
 
MMIO offset 3F0h (n/a)
MSR 0000_083Fh (WO)
reserved vector
AMD / optional
EXT_APIC_FEAT
 
MMIO offset 400h (RO)
MSR 0000_0840h (RO)
reserved extended LVT count reserved Ext
A
ID
AVL
Spe
cific
EOI
AVL
Int
En
Reg
AVL
AMD / optional
EXT_APIC_CTRL
 
MMIO offset 410h (RW)
MSR 0000_0841h (RW)
reserved Ext
A
ID
EN
Spe
cific
EOI
EN
Int
En
Reg
EN
AMD / optional
EXT_APIC_SEOI
 
MMIO offset 420h (RW)
MSR 0000_0842h (RW)
reserved vector
AMD / optional
EXT_APIC_IER
 
MMIO offset 480h (RW)
MSR 0000_0848h (RW)
 
...
 
MMIO offset 4F0h (RW)
MSR 0000_084Fh (RW)
... 1
6
 
reserved
 
2
5
5
...
AMD / optional
EXT_APIC_LVT_0
 
MMIO offset 500h (RW)
MSR 0000_0850h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

0=fix 1=lp 2=S
3=rr 4=N 5=IN
6=SIPI 7=ExtI
vector
AMD / optional
EXT_APIC_LVT_1
 
MMIO offset 510h (RW)
MSR 0000_0851h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

0=fix 1=lp 2=S
3=rr 4=N 5=IN
6=SIPI 7=ExtI
vector
AMD / optional
EXT_APIC_LVT_2
 
MMIO offset 520h (RW)
MSR 0000_0852h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

0=fix 1=lp 2=S
3=rr 4=N 5=IN
6=SIPI 7=ExtI
vector
AMD / optional
EXT_APIC_LVT_3
 
MMIO offset 530h (RW)
MSR 0000_0853h (RW)
reserved M
A
S
K
reserved DS

idle
or
pen
r. DEST MODE

0=fix 1=lp 2=S
3=rr 4=N 5=IN
6=SIPI 7=ExtI
vector
note description
TPR TPR[7...4] = CR8.[3...0] – SW should use one or the other – SW must explicitly serialize if it mixes both



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© 1996-2024 by Christian Ludloff. All rights reserved. Use at your own risk.