x86 architecture
canonical addresses


 
in LM all unsupported virtual address bits must be sign-extended
 
virtual
address
bits		 6
3		 6
2		 6
1		 6
0		 5
9		 5
8		 5
7		 5
6		 5
5		 5
4		 5
3		 5
2		 5
1		 5
0		 4
9		 4
8		 4
7		 4
6		 4
5		 4
4		 4
3		 4
2		 4
1		 4
0		 3
9		 3
8		 3
7		 3
6		 3
5		 3
4		 3
3		 3
2		 3
1		   0
 
32
 		 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  xxx 
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  xxx 
 
48 #1
 		 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  xxx 
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1  xxx 
 
57 #2
 		 0 0 0 0 0 0 0 0  xxx 
1 1 1 1 1 1 1 1  xxx 
 
64
 		  xxx 
 xxx 
note description
#1 The 4-level paging VA48 implementation supports 48 virtual address bits, resulting in the following regions:
 
begin end canonical?
0000_0000_0000_0000h 0000_7FFF_FFFF_FFFFh yes
0000_8000_0000_0000h FFFF_7FFF_FFFF_FFFFh no, causes #GP(0) or #SS(0)
FFFF_8000_0000_0000h FFFF_FFFF_FFFF_FFFFh yes
 
#2 The 5-level paging VA57 implementation supports 57 virtual address bits, resulting in the following regions:
 
begin end canonical?
0000_0000_0000_0000h 00FF_FFFF_FFFF_FFFFh yes
0100_0000_0000_0000h FEFF_FFFF_FFFF_FFFFh no, causes #GP(0) or #SS(0)
FF00_0000_0000_0000h FFFF_FFFF_FFFF_FFFFh yes
 


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