rFLAGS register
| 16/32/64-bit FLAGS/EFLAGS/RFLAGS register |
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| 6 3 |
6 2 |
6 1 |
6 0 |
5 9 |
5 8 |
5 7 |
5 6 |
5 5 |
5 4 |
5 3 |
5 2 |
5 1 |
5 0 |
4 9 |
4 8 |
4 7 |
4 6 |
4 5 |
4 4 |
4 3 |
4 2 |
4 1 |
4 0 |
3 9 |
3 8 |
3 7 |
3 6 |
3 5 |
3 4 |
3 3 |
3 2 |
| 3 1 |
3 0 |
2 9 |
2 8 |
2 7 |
2 6 |
2 5 |
2 4 |
2 3 |
2 2 |
2 1 |
2 0 |
1 9 |
1 8 |
1 7 |
1 6 |
1 5 |
1 4 |
1 3 |
1 2 |
1 1 |
1 0 |
9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RX 32 |
XC XR XY XP XT |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | I D |
V I P |
V I F |
A C |
V M |
R F |
0 | N T |
IOPL | O F |
D F |
I F |
T F |
S F |
Z F |
0 | A F |
0 | P F |
1 | C F |
|
note: Do not rely on undefined integer FLAGS behavior.
| undefined integer FLAGS behavior |
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| instruction | P5 core | P6 core#0 | P4 core | case | ||||||||||||||||||
| OF | SF | ZF | AF | PF | CF | OF | SF | ZF | AF | PF | CF | OF | SF | ZF | AF | PF | CF | |||||
| AAA | OF16 | SF16 | ZF16 | M | PF | M | U | 0 | ZF16 | M | PF | M | 0 | 0 | ZF8 | M | PF | M | ||||
| AAS | #1 | |||||||||||||||||||||
| AAM | 0 | M | M | 0 | M | 0 | 0 | M | M | 0 | M | 0 | 0 | M | M | 0 | M | 0 | ||||
| AAD | OF8 | AF | CF | OF8 | AF | CF | ||||||||||||||||
| DAA | OF8 | M | M | M | M | M | U | M | M | M | M | M | 0 | M | M | M | M | M | ||||
| DAS | ||||||||||||||||||||||
| AND, OR, TEST, XOR | 0 | M | M | 0 | M | 0 | 0 | M | M | 0 | M | 0 | 0 | M | M | 0 | M | 0 | ||||
| (I)MUL | M | U | U | U | U | M | M | U | U | U | U | M | M | SF | ZF | 0 | PF | M | ||||
| (I)DIV | ? | ? | ? | ? | ? | ? | U | U | U | U | U | U | U | U | U | U | U | U | ||||
| F(U)COMI(P) | not supported | 0 | 0 | M | 0 | M | M | 0 | 0 | M | 0 | M | M | |||||||||
| BT, BTC, BTR, BTS | #2 | U | U | U | U | M | U | U | U | U | U | M | U | U | U | U | U | M | ||||
| BSF | 0 | 0 | M | ? | 1 | 0 | U | U | M | U | U | U | 0 | 0 | M | 0 | 1 | 0 | src=0 | |||
| BSF | ? | ? | ? | ? | PF | src<>0 | ||||||||||||||||
| BSR | 0 | 0 | 1 | 1 | 0 | 1 | src=0 | |||||||||||||||
| BSR | ? | ? | ? | ? | PF | src<>0 | ||||||||||||||||
| ROL and ROR | OFx | U | U | U | U | M | U | U | U | U | U | M | #3 | U | U | U | U | M | >1 | |||
| RCL and RCR | OFx | U | U | U | U | M | #4 | U | U | U | U | M | #3 | U | U | U | U | M | >1 | |||
| SHL and SHR SAL and SAR |
M | M | M | 1 | M | M | M | M | M | U | M | M | M | M | M | 0 | M | M | 1 | |||
| OFx | M | M | M | M | U | M | M | M | M | OFx | M | M | M | M | 2...N | |||||||
| M | M | M | CF #5 |
M | M | M | CF #6 |
M | M | M | CF | >N | ||||||||||
| SHLD and SHRD #7 | M | M | M | 1 | M | M | M | M | M | U | M | M | M | M | M | 0 | M | M | 1 | |||
| OFx | M | M | M | M | U | M | M | M | M | OFx | M | M | M | M | 2...N | |||||||
| SF | ZF | PF | CF | SF | ZF | PF | CF | SF | ZF | PF | CF | >N | ||||||||||
| notes | descriptions | |||||||||||||||||||||
| #0 |
except for Pentium Pro: TEST (AF=U) -- this is considered an outlier which got fixed in the P2 except for Core 2: AAA (OF=1), AAS (OF=0), DAA (OF=0), DAS (OF=0) -- instead of OF=U |
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| #1 | if (((AL & 0Fh) > 09h) | (AF = 1)) { PF[AL+06h] } else { PF[AL] } | |||||||||||||||||||||
| #2 | as if a ROR was performed, i.e. OFR | |||||||||||||||||||||
| #3 |
U if size=0, else OFx ROL/ROR size = (count & 1Fh) RCL/RCR size = (count & 1Fh) % (N+1) |
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| #4 |
U if dword, else U if size>1, else OFx RCL/RCR size = (count & 1Fh) % (N+1) |
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| #5 | ? for SHR/SHL/SAL byte with count=16 or count=24 | |||||||||||||||||||||
| #6 | for SHR byte: if (MSB[dst] = 1) & (((count & 1Fh) % 8) = 0) { 1 } else { 0 } | |||||||||||||||||||||
| #7 |
P5 uses dst:src:SRC for SHLD, and SRC:src:dst for SHRD P6 uses dst:src:DST for SHLD, and DST:src:dst for SHRD P4 uses dst:src:DST for SHLD, and DST:src:dst for SHRD |
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© 1996-2024 by Christian Ludloff. All rights reserved. Use at your own risk.