x86 architecture initial state   initial processor state after RESET and INIT   general purpose registers after RESET after INIT RAX 0000_0000_0000_0000h or BIST result 0000_0000_0000_0000h or BIST result RBX 0000_0000_0000_0000h 0000_0000_0000_0000h RCX 0000_0000_0000_0000h 0000_0000_0000_0000h RDX 0000_0000_0ffm_TFMSh (see CPUID) 0000_0000_0ffm_TFMSh (see CPUID) RSP 0000_0000_0000_0000h 0000_0000_0000_0000h RBP 0000_0000_0000_0000h 0000_0000_0000_0000h RSI 0000_0000_0000_0000h 0000_0000_0000_0000h RDI 0000_0000_0000_0000h 0000_0000_0000_0000h R8...R15 0000_0000_0000_0000h 0000_0000_0000_0000h R16...R31 0000_0000_0000_0000h unchanged RIP 0000_0000_0000_FFF0h 0000_0000_0000_FFF0h flags register after RESET after INIT RFLAGS 0000_0000_0000_0002h 0000_0000_0000_0002h bounds registers after RESET after INIT BND0...BND3 upper=0000_0000_0000_0000h lower=0000_0000_0000_0000h upper=0000_0000_0000_0000h lower=0000_0000_0000_0000h BNDCFGS 0000_0000_0000_0000h 0000_0000_0000_0000h BNDCFGU 0000_0000_0000_0000h 0000_0000_0000_0000h BNDSTATUS 0000_0000_0000_0000h 0000_0000_0000_0000h CET registers after RESET after INIT SSP 0000_0000_0000_0000h 0000_0000_0000_0000h PL0_SSP 0000_0000_0000_0000h 0000_0000_0000_0000h PL1_SSP 0000_0000_0000_0000h 0000_0000_0000_0000h PL2_SSP 0000_0000_0000_0000h 0000_0000_0000_0000h PL3_SSP 0000_0000_0000_0000h 0000_0000_0000_0000h IST_SSP 0000_0000_0000_0000h 0000_0000_0000_0000h S_CET 0000_0000_0000_0000h 0000_0000_0000_0000h U_CET 0000_0000_0000_0000h 0000_0000_0000_0000h segment registers after RESET after INIT CS selector=F000h base=FFFF_0000h limit=0000_FFFFh access rights=0093h, writeable selector=F000h base=FFFF_0000h limit=0000_FFFFh access rights=0093h, writeable SS selector=0000h base=0000_0000h limit=0000_FFFFh access rights=0093h selector=0000h base=0000_0000h limit=0000_FFFFh access rights=0093h DS selector=0000h base=0000_0000h limit=0000_FFFFh access rights=0093h selector=0000h base=0000_0000h limit=0000_FFFFh access rights=0093h ES selector=0000h base=0000_0000h limit=0000_FFFFh access rights=0093h selector=0000h base=0000_0000h limit=0000_FFFFh access rights=0093h FS selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0093h selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0093h GS selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0093h selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0093h table registers after RESET after INIT GDTR base=0000_0000_0000_0000h limit=0000_FFFFh (access rights=0082h) base=0000_0000_0000_0000h limit=0000_FFFFh (access rights=0082h) IDTR base=0000_0000_0000_0000h limit=0000_FFFFh (access rights=0082h) base=0000_0000_0000_0000h limit=0000_FFFFh (access rights=0082h) LDTR selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0082h selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0082h TR selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0082h selector=0000h base=0000_0000_0000_0000h limit=0000_FFFFh access rights=0082h control registers after RESET after INIT CR0 0000_0000_6000_0010h 0000_0000_x000_0010h #1 CR2 0000_0000_0000_0000h 0000_0000_0000_0000h CR3 0000_0000_0000_0000h 0000_0000_0000_0000h CR4 0000_0000_0000_0000h 0000_0000_0000_0000h CR8 0000_0000_0000_0000h unchanged XSS 0000_0000_0000_0000h unchanged XCR0 0000_0000_0000_0001h unchanged PKRU 0000_0000_0000_0000h unchanged PKRS 0000_0000_0000_0000h unchanged debug registers after RESET after INIT DR0 0000_0000_0000_0000h 0000_0000_0000_0000h DR1 0000_0000_0000_0000h 0000_0000_0000_0000h DR2 0000_0000_0000_0000h 0000_0000_0000_0000h DR3 0000_0000_0000_0000h 0000_0000_0000_0000h DR6 0000_0000_FFFF_0FF0h 0000_0000_FFFF_0FF0h DR7 0000_0000_0000_0400h 0000_0000_0000_0400h legacy FP registers after RESET after INIT ST0...ST7 +0.0 unchanged (80486 without BIST) unchanged MM0...MM7 0000_0000_0000_0000h unchanged CW 0040h 037Fh (8087 and 80287) IM=0 (80387 permitting ERROR#) 037Fh (80486 with BIST) unchanged (80486 without BIST) The 80287 forces its ERROR# output inactive after RESET. The 80387 forces its ERROR# output active after RESET. The 80386 relies on that difference to distinguish them. The CR0.ET bit captures it and controls the interface. 0 = 16-bit 80287 protocol. 1 = 32-bit 80387 protocol. Note: 0 can also mean that no coprocessor is present, or that an 80387 is present but connected in a non-standard manner such as in the PC/AT-compatible design. (You can adjust ET.) The 80486, like the 80287, does not signal an error after RESET. The 80486, however, only initializes the FPU when BIST is used. unchanged SW 0000h IE=ES=B=1 (80387 signaling ERROR#) unchanged (80486 without BIST) unchanged TW 5555h FFFFh (8087 and 80287) FFFFh (80387) FFFFh (80486 with BIST) unchanged (80486 without BIST) unchanged FP_IP64 0000:0000_0000_0000_0000h unchanged (80486 without BIST) unchanged FP_DP64 0000:0000_0000_0000_0000h unchanged (80486 without BIST) unchanged FP_OPC 000_0000_0000b unchanged (80486 without BIST) unchanged vector FP registers after RESET after INIT XMM0...XMM7 0h unchanged XMM8...XMM15 0h unchanged XMM16...XMM31 0h unchanged YMM0...YMM7 0h unchanged YMM8...YMM15 0h unchanged YMM16...YMM31 0h unchanged ZMM0...ZMM7 0h unchanged ZMM8...ZMM15 0h unchanged ZMM16...ZMM31 0h unchanged MXCSR 0000_1F80h 0020_0000h (K1OM) unchanged mask registers after RESET after INIT K0...K7 0000_0000_0000_0000h unchanged Time Stamp Counter after RESET after INIT TSC 0000_0000_0000_0000h unchanged TSC_ADJUST 0000_0000_0000_0000h unchanged TSC_AUX 0000_0000h unchanged TSC_DEADLINE 0000_0000_0000_0000h unchanged MPERF 0000_0000_0000_0000h unchanged APERF 0000_0000_0000_0000h unchanged Feature Control after RESET after INIT Intel P5 TR12 ITR unknown unchanged MISC_ENABLE processor-specific unchanged PREFETCH_CTRL processor-specific unchanged CODE_PREFETCH_CTRL processor-specific unchanged CORE_CAPABILITIES processor-specific unchanged MEMORY_CTRL processor-specific unchanged EFER 0000_0000h 0000_0000h if non-intercepted and non-redirected: SVME=0 AMD HWCR processor-specific unchanged PLATFORM_INFO processor-specific unchanged MISC_FEATURES processor-specific unchanged Speculation Control after RESET after INIT ARCH_CAPABILITIES processor-specific unchanged SPEC_CTRL 0000_0000_0000_0000h unchanged PRED_CMD n/a (write-only) n/a (write-only) FLUSH_CMD n/a (write-only) n/a (write-only) MCU_OPT_CTRL 0000_0000_0000_0000h unchanged TSX_CTRL 0000_0000_0000_0000h unchanged TSX_FORCE_ABORT 0000_0000_0000_0001h unchanged UARCH_MISC_CTRL 0000_0000_0000_0000h unchanged PSN or PPIN after RESET after INIT PSN_CTL PSN enabled unchanged PPIN_CTL processor-specific unchanged PPIN processor-specific unchanged SYSENTER and SYSEXIT after RESET after INIT SEP_SEL 0000h unchanged SEP_RSP 0000_0000_0000_0000h unchanged SEP_RIP 0000_0000_0000_0000h unchanged SYSCALL and SYSRET after RESET after INIT STAR 0000_0000_0000_0000h unchanged LSTAR 0000_0000_0000_0000h unchanged CSTAR 0000_0000_0000_0000h unchanged FMASK 0000_0000h unchanged FS base and GS base after RESET after INIT FS_BAS 0000_0000_0000_0000h 0000_0000_0000_0000h GS_BAS 0000_0000_0000_0000h 0000_0000_0000_0000h KERNEL_GS_BAS 0000_0000_0000_0000h 0000_0000_0000_0000h PAT and MTRRs after RESET after INIT PAT 0007_0406_0007_0406h unchanged MTRR_CAP processor-specific unchanged MTRR_DEF_TYPE 0000_0000_0000_0000h unchanged MTRR_FIX_* undefined (P6) 0000_0000_0000_0000h (P4+) unchanged MTRR_PHYS_* 0000_0000_0000_0000h unchanged SMRR_PHYS_* 0000_0000_0000_0000h unchanged Machine Check Exception after RESET after INIT MCAR 0000_0000h unchanged MCTR 0000_0000h unchanged Machine Check Architecture after RESET after INIT MCG_CONTAIN cold: 0000_0000_0000_0000h warm: unchanged unchanged MCG_CAP processor-specific unchanged MCG_STATUS note: some bits may be hard-wired to 1 cold: 0000_0000_0000_0000h warm: unchanged unchanged MCG_CTL cold: 0000_0000_0000_0000h warm: unchanged unchanged MCG_EXT_CTL cold: 0000_0000_0000_0000h warm: unchanged unchanged MCA Error-Reporting Banks after RESET after INIT MCn_CTL cold: 0000_0000_0000_0000h warm: unchanged unchanged MCn_CTL2 cold: 0000_0000_0000_0000h warm: unchanged unchanged MCn_STATUS note: some bits may be hard-wired to 1 cold: 0000_0000_0000_0000h warm: unchanged unchanged MCn_ADDR cold: 0000_0000_0000_0000h warm: unchanged unchanged MCn_MISC cold: 0000_0000_0000_0000h warm: unchanged unchanged MCA Extended State Regs after RESET after INIT MCG_* cold: 0000_0000_0000_0000h warm: unchanged unchanged Local APIC after RESET after INIT APIC_BASE FEE0_0x00h (x=9 if BSP, else x=8) unchanged XAPIC_DISABLE_STATUS processor-specific unchanged miscellaneous after RESET after INIT PASID 0000_0000_0000_0000h unchanged SMM related internal regs after RESET after INIT SMBASE 0003_0000h unchanged IO_RESTART_RIP 0000_0000_0000_0000h unchanged IO_RESTART_RCX 0000_0000_0000_0000h unchanged IO_RESTART_RSI 0000_0000_0000_0000h unchanged IO_RESTART_RDI 0000_0000_0000_0000h unchanged additional internal flags after RESET after INIT TEMP_DR6 0000_0000_0000_0000h 0000_0000_0000_0000h CAUSING_DB false false BLOCK_INIT false n/a BLOCK_SMI false false BLOCK_NMI false false LATCH_INIT false n/a LATCH_SMI false false LATCH_NMI false false IN_REP false false IN_SMM false false IN_HLT false false IN_SHUTDOWN false false IN_FP_FREEZE false false SUPPRESS_INTERRUPTS false (both bits) false (both bits) legacy stuff after RESET after INIT A20M# deasserted high KBC=flat PS/2=pass unchanged (old) or deasserted high (new) KBC=unchanged PS/2=unchanged (old) or flat (new) FERR# deasserted high unchanged internal buffers after RESET after INIT processor caches invalidated unchanged TLBs, BPs, etc. invalidated invalidated PDPTR0/1/2/3 zero zero APIC after RESET after INIT ID unique unchanged VER 00nn00vvh (Intel) or 80nn00vvh (AMD) unchanged TPR 0000_0000h 0000_0000h APR 0000_0000h 0000_0000h PPR 0000_0000h 0000_0000h EOI n/a (write-only) n/a (write-only) RRR 0000_0000h 0000_0000h LDR 0000_0000h 0000_0000h DFR all 1s all 1s SVR 0000_00FFh 0000_00FFh ISR all 0s all 0s TMR all 0s all 0s IRR all 0s all 0s TEMP_ESR 0000_0000h 0000_0000h ESR 0000_0000h 0000_0000h ICR 0000_0000_0000_0000h 0000_0000_0000_0000h LVT_ERROR 0001_0000h 0001_0000h LVT_TIMER 0001_0000h 0001_0000h LVT_LINT0 0001_0000h 0001_0000h LVT_LINT1 0001_0000h 0001_0000h LVT_PMC 0001_0000h 0001_0000h LVT_THERMAL 0001_0000h 0001_0000h LVT_CMCI 0001_0000h 0001_0000h TIMER_ICR 0000_0000h 0000_0000h TIMER_CCR 0000_0000h 0000_0000h TIMER_DCR 0000_0000h 0000_0000h SELF_IPI n/a (write-only) n/a (write-only) EXT_APIC_FEAT 0004_0007h 0004_0007h EXT_APIC_CTRL 0000_0000h 0000_0000h EXT_APIC_SEOI n/a (write-only) n/a (write-only) EXT_APIC_IER all 1s all 1s EXT_APIC_LVT_0 0000_0000h 0000_0000h EXT_APIC_LVT_1 0000_0000h 0000_0000h EXT_APIC_LVT_2 0000_0000h 0000_0000h EXT_APIC_LVT_3 0000_0000h 0000_0000h note description #1 bits 30 (CD) and 29 (NW) remain unchanged © 1996-2024 by Christian Ludloff. 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