opcode groups
note: A leading bold V indicates that the instruction can be VEX-encoded, in which case it may have additional operands.
note: A leading bold ! indicates that the 256-bit version was only introduced with AVX2 and that it can only be VEX-encoded.
note: AVX10.1 is comprised of AVX512{F,CD,BW,DQ,VL,IFMA,VBMI,VNNI,BF16,VBMI2,BITALG,VPOPCNTDQ,FP16} and
of the EVEX-encoded variants of VAES, GFNI, and VPCLMUL, but not AVX512{PF,ER,QFMA,QVNNIW,VP2INTERSECT}.
AVX512QVNNI didn't ship in KNM as originally planned. AVX512DFMA and AVX512BITALG2 were specified but didn't ship.
note: AVX10.2 is comprised of {BF16,COMX,CVTFP8,DP,SAD,MINMAX,CVTS,VMOV} and 256-bit {er} and {sae} variants.
note: A leading bold !! indicates that the 256-bit {er} or {sae} variant, encoded with U=0, was only introduced with AVX10.2.
note: Although SM4-EVEX, VMOVRS* from MOVRS, and AMX-AVX512 depend on AVX10.2, they are not part of AVX10.2.
| mod R/M |
|
xx000xxx | xx001xxx | xx010xxx | xx011xxx | xx100xxx | xx101xxx | xx110xxx | xx111xxx |
| group #1 (80h) |
|
ADD Eb,Ib | OR Eb,Ib | ADC Eb,Ib | SBB Eb,Ib | AND Eb,Ib | SUB Eb,Ib | XOR Eb,Ib | CMP Eb,Ib |
| group #1 (81h) |
|
ADD Ev,Iz | OR Ev,Iz | ADC Ev,Iz | SBB Ev,Iz | AND Ev,Iz | SUB Ev,Iz | XOR Ev,Iz | CMP Ev,Iz |
| group #1 (82h) |
|
ADD* Eb,IbI64 | OR* Eb,IbI64 | ADC* Eb,IbI64 | SBB* Eb,IbI64 | AND* Eb,IbI64 | SUB* Eb,IbI64 | XOR* Eb,IbI64 | CMP* Eb,IbI64 |
| group #1 (83h) |
|
ADD Ev,Ib | OR Ev,Ib | ADC Ev,Ib | SBB Ev,Ib | AND Ev,Ib | SUB Ev,Ib | XOR Ev,Ib | CMP Ev,Ib |
| group #1 (EVEX NP) (MAP4 80h) |
|
{NF} ADD {ND} Bb,Eb,Ib |
{NF} OR {ND} Bb,Eb,Ib |
ADC {ND} Bb,Eb,Ib |
SBB {ND} Bb,Eb,Ib |
{NF} AND {ND} Bb,Eb,Ib |
{NF} SUB {ND} Bb,Eb,Ib |
{NF} XOR {ND} Bb,Eb,Ib |
CMPscc Eb,Ib,dfv |
| group #1 (EVEX NP+66) (MAP4 81h) |
|
{NF} ADD {ND} Bv,Ev,Iz |
{NF} OR {ND} Bv,Ev,Iz |
ADC {ND} Bv,Ev,Iz |
SBB {ND} Bv,Ev,Iz |
{NF} AND {ND} Bv,Ev,Iz |
{NF} SUB {ND} Bv,Ev,Iz |
{NF} XOR {ND} Bv,Ev,Iz |
CMPscc Ev,Iz,dfv |
| group #1 (EVEX NP) (MAP4 82h) |
|
(no 80h alias) | (no 80h alias) | (no 80h alias) | (no 80h alias) | (no 80h alias) | (no 80h alias) | (no 80h alias) | (no 80h alias) |
| group #1 (EVEX NP+66) (MAP4 83h) |
|
{NF} ADD {ND} Bv,Ev,Ib |
{NF} OR {ND} Bv,Ev,Ib |
ADC {ND} Bv,Ev,Ib |
SBB {ND} Bv,Ev,Ib |
{NF} AND {ND} Bv,Ev,Ib |
{NF} SUB {ND} Bv,Ev,Ib |
{NF} XOR {ND} Bv,Ev,Ib |
CMPscc Ev,Ib,dfv |
| group #1A (8Fh) |
|
POPD64 Ev | XOP (000b) XOP (001b) XOP (010b) |
||||||
| group #1 (EVEX NP) (MAP4 8Fh) |
|
{ND} POP2 F64 (W=0) Bq,Rq !RSP {ND} POP2PF64 (W=1) Bq,Rq !RSP |
(not XOP) | ||||||
| group #2 (C0h) (80186+) |
|
ROL Eb,Ib | ROR Eb,Ib | RCL Eb,Ib | RCR Eb,Ib | SHL Eb,Ib | SHR Eb,Ib | SAL* Eb,Ib | SAR Eb,Ib |
| group #2 (C1h) (80186+) |
|
ROL Ev,Ib | ROR Ev,Ib | RCL Ev,Ib | RCR Ev,Ib | SHL Ev,Ib | SHR Ev,Ib | SAL* Ev,Ib | SAR Ev,Ib |
| group #2 (D0h) |
|
ROL Eb,1 | ROR Eb,1 | RCL Eb,1 | RCR Eb,1 | SHL Eb,1 | SHR Eb,1 | SAL* Eb,1 | SAR Eb,1 |
| group #2 (D1h) |
|
ROL Ev,1 | ROR Ev,1 | RCL Ev,1 | RCR Ev,1 | SHL Ev,1 | SHR Ev,1 | SAL* Ev,1 | SAR Ev,1 |
| group #2 (D2h) |
|
ROL Eb,CL | ROR Eb,CL | RCL Eb,CL | RCR Eb,CL | SHL Eb,CL | SHR Eb,CL | SAL* Eb,CL | SAR Eb,CL |
| group #2 (D3h) |
|
ROL Ev,CL | ROR Ev,CL | RCL Ev,CL | RCR Ev,CL | SHL Ev,CL | SHR Ev,CL | SAL* Ev,CL | SAR Ev,CL |
| group #2 (EVEX NP) (MAP4 C0h) |
|
{NF} ROL {ND} Bb,Eb,Ib |
{NF} ROR {ND} Bb,Eb,Ib |
RCL {ND} Bb,Eb,Ib |
RCR {ND} Bb,Eb,Ib |
{NF} SHL {ND} Bb,Eb,Ib |
{NF} SHR {ND} Bb,Eb,Ib |
{NF} SAL* {ND} Bb,Eb,Ib |
{NF} SAR {ND} Bb,Eb,Ib |
| group #2 (EVEX NP+66) (MAP4 C1h) |
|
{NF} ROL {ND} Bv,Ev,Ib |
{NF} ROR {ND} Bv,Ev,Ib |
RCL {ND} Bv,Ev,Ib |
RCR {ND} Bv,Ev,Ib |
{NF} SHL {ND} Bv,Ev,Ib |
{NF} SHR {ND} Bv,Ev,Ib |
{NF} SAL* {ND} Bv,Ev,Ib |
{NF} SAR {ND} Bv,Ev,Ib |
| group #2 (EVEX NP) (MAP4 D0h) |
|
{NF} ROL {ND} Bb,Eb,1 |
{NF} ROR {ND} Bb,Eb,1 |
RCL {ND} Bb,Eb,1 |
RCR {ND} Bb,Eb,1 |
{NF} SHL {ND} Bb,Eb,1 |
{NF} SHR {ND} Bb,Eb,1 |
{NF} SAL* {ND} Bb,Eb,1 |
{NF} SAR {ND} Bb,Eb,1 |
| group #2 (EVEX NP+66) (MAP4 D1h) |
|
{NF} ROL {ND} Bv,Ev,1 |
{NF} ROR {ND} Bv,Ev,1 |
RCL {ND} Bv,Ev,1 |
RCR {ND} Bv,Ev,1 |
{NF} SHL {ND} Bv,Ev,1 |
{NF} SHR {ND} Bv,Ev,1 |
{NF} SAL* {ND} Bv,Ev,1 |
{NF} SAR {ND} Bv,Ev,1 |
| group #2 (EVEX NP) (MAP4 D2h) |
|
{NF} ROL {ND} Bb,Eb,CL |
{NF} ROR {ND} Bb,Eb,CL |
RCL {ND} Bb,Eb,CL |
RCR {ND} Bb,Eb,CL |
{NF} SHL {ND} Bb,Eb,CL |
{NF} SHR {ND} Bb,Eb,CL |
{NF} SAL* {ND} Bb,Eb,CL |
{NF} SAR {ND} Bb,Eb,CL |
| group #2 (EVEX NP+66) (MAP4 D3h) |
|
{NF} ROL {ND} Bv,Ev,CL |
{NF} ROR {ND} Bv,Ev,CL |
RCL {ND} Bv,Ev,CL |
RCR {ND} Bv,Ev,CL |
{NF} SHL {ND} Bv,Ev,CL |
{NF} SHR {ND} Bv,Ev,CL |
{NF} SAL* {ND} Bv,Ev,CL |
{NF} SAR {ND} Bv,Ev,CL |
| group #3 (F6h) |
|
TEST Eb,Ib | TEST* Eb,Ib | NOT Eb | NEG Eb | MUL Eb | IMUL Eb | DIV Eb | IDIV Eb |
| group #3 (F7h) |
|
TEST Ev,Iz | TEST* Ev,Iz | NOT Ev | NEG Ev | MUL Ev | IMUL Ev | DIV Ev | IDIV Ev |
| group #3 (EVEX NP) (MAP4 F6h) |
|
CTESTscc Eb,Ib,dfv |
CTESTscc* Eb,Ib,dfv |
NOT {ND} Bb,Eb |
{NF} NEG {ND} Bb,Eb |
{NF} MUL Eb |
{NF} IMUL Eb |
{NF} DIV Eb |
{NF} IDIV Eb |
| group #3 (EVEX NP+66) (MAP4 F7h) |
|
CTESTscc Ev,Iz,dfv |
CTESTscc* Ev,Iz,dfv |
NOT {ND} Bv,Ev |
{NF} NEG {ND} Bv,Ev |
{NF} MUL Ev |
{NF} IMUL Ev |
{NF} DIV Ev |
{NF} IDIV Ev |
| group #4 (FEh) |
|
INC Eb | DEC Eb | ||||||
| group #4 (EVEX NP) (MAP4 FEh) |
|
{NF} INC {ND} Bb,Eb |
{NF} DEC {ND} Bb,Eb |
||||||
| group #4 (EVEX 66) (MAP4 FEh) |
|
||||||||
| group #5 (FFh) |
|
INC Ev | DEC Ev | CALLDf64 Ev | CALL Mp (w:z) (or call gate's y) Intel: (w:v) |
JMPDf64 Ev | JMP Mp (w:z) (or call gate's y) Intel: (w:v) |
PUSHD64 Ev | UD (FFh) (80186+) |
| group #5 (EVEX NP) (MAP4 FFh) |
|
{NF} INC {ND} Bv,Ev |
{NF} DEC {ND} Bv,Ev |
{ND} PUSH2 F64 (W=0) Bq,Rq !RSP {ND} PUSH2PF64 (W=1) Bq,Rq !RSP |
|||||
| group #5 (EVEX 66) (MAP4 FFh) |
|
||||||||
| group #6 (0Fh,00h) |
|
SLDT Mw | STR Mw | LLDT Mw | LTR Mw | VERR Mw | 👻 VERW Mw 👻 |
(n/a) JMPE Ev (IA-64) (66h) JMPE Ev (IA-64) (F3h) don't allocate (in #UD use) (F2h) LKGS Mw/Rv (see CPUID) |
|
| |
SLDT Rv | STR Rv | LLDT Rv | LTR Rv | VERR Rv | VERW Rv | |||
| group #7 (0Fh,01h) |
|
SGDTF64 Mp (w:y) |
SIDTF64 Mp (w:y) |
LGDTF64 Mp (w:y) |
LIDTF64 Mp (w:y) |
SMSW Mw | (F3h) RSTORSSP Mq (see CPUID) |
LMSW Mw | INVLPG M (80486+) |
| (n/a) | |||||||||
|
ENCLV (C0h) VMCALL (C1h) VMLAUNCH (C2h) VMRESUME (C3h) VMXOFF (C4h) PCONFIG (C5h) WRMSRNS (C6h) PBNDKB (C7h) (see CPUID) |
MONITOR (C8h) MWAIT (C9h) CLAC (CAh) STAC (CBh) ENCLS (CFh) (see CPUID) |
XGETBV (D0h) XSETBV (D1h) VMFUNC (D4h) XEND (D5h) XTEST (D6h) ENCLU (D7h) (see CPUID) |
VMRUN (D8h) VMMCALL (D9h) VMLOAD (DAh) VMSAVE (DBh) STGI (DCh) CLGI (DDh) SKINIT (DEh) INVLPGA (DFh) (see CPUID) |
SMSW Rv |
SERIALIZE (E8h) RDPKRU (EEh) WRPKRU (EFh) (see CPUID) |
LMSW Rv |
SWAPGS (F8h) RDTSCP (F9h) MONITORX (FAh) MWAITX (FBh) CLZERO (FCh) RDPRU (FDh) INVLPGB (FEh) TLBSYNC (FFh) (see CPUID) |
||
| (66h) | |||||||||
|
(see CPUID) |
TDCALL (CCh) SEAMRET (CDh) SEAMOPS (CEh) SEAMCALL (CFh) (see CPUID) |
(see CPUID) |
(see CPUID) |
SMSW Rv |
(see CPUID) |
LMSW Rv |
(see CPUID) |
||
| (F3h) | |||||||||
|
WRMSRLIST (C6h) (see CPUID) |
ERETU (CAh) (see CPUID) |
(see CPUID) |
VMGEXIT (D9h) (see CPUID) |
SMSW Rv |
SETSSBSY (E8h) SAVEprevSSP(EAh) UIRET (ECh) TESTUI (EDh) CLUI (EEh) STUI (EFh) (see CPUID) |
LMSW Rv |
MCOMMIT (FAh) RMPQUERY (FDh) RMPADJUST (FEh) PSMASH (FFh) (see CPUID) |
||
| (F2h) | |||||||||
|
RDMSRLIST (C6h) (see CPUID) |
ERETS (CAh) (see CPUID) |
(see CPUID) |
VMGEXIT (D9h) (see CPUID) |
SMSW Rv |
XSUSLDTRK (E8h) XRESLDTRK (E9h) (see CPUID) |
LMSW Rv |
RMPREAD (FDh) RMPUPDATE (FEh) PVALIDATE (FFh) (see CPUID) |
||
| group #8 (0Fh,BAh) (80386+) |
|
BT Ev,Ib | BTS Ev,Ib | BTR Ev,Ib | BTC Ev,Ib | ||||
| group #9 (0Fh,C7h) |
|
CMPXCHG8B Mq CMPXCHG16B Mo (see CPUID) |
APX! XRSTORS M (see CPUID) |
APX! XSAVEC M (see CPUID) |
APX! XSAVES M (see CPUID) |
(n/a) VMPTRLD Mq (66h) VMCLEAR Mq (F3h) VMXON Mq (see CPUID) |
(n/a) VMPTRST Mq (see CPUID) |
||
| |
(n/a) RDRAND Rv (66h) RDRAND Rv (F3h) SENDUIPI Rq (see CPUID) |
(n/a) RDSEED Rv (66h) RDSEED Rv (F3h) RDPID Ry (see CPUID) |
|||||||
| group #10 (0Fh,B9h) |
|
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
UD1 /r AMD APM: /r is not fetched by all chips |
| group #11 (C6h) |
|
MOV Eb,Ib |
XABORT Ib (F8h) (see CPUID) |
||||||
| group #11 (C7h) |
|
MOV Ev,Iz |
XBEGIN Jz (F8h) (see CPUID) |
||||||
| group #12 (0Fh,71h) |
|
PSRLW Nq,Ib (MMX) (66h) !VPSRLW Hx,Ux,Ib (SSE2) |
PSRAW Nq,Ib (MMX) (66h) !VPSRAW Hx,Ux,Ib (SSE2) |
PSLLW Nq,Ib (MMX) (66h) !VPSLLW Hx,Ux,Ib (SSE2) |
|||||
| group #12 (EVEX 66h) (0Fh,71h) |
|
VPSRLW Hn {K} {z}, Wn,Ib (W=x) (AVX512BW,VL) |
VPSRAW Hn {K} {z}, Wn,Ib (W=x) (AVX512BW,VL) |
VPSLLW Hn {K} {z}, Wn,Ib (W=x) (AVX512BW,VL) |
|||||
| group #13 (0Fh,72h) |
|
PSRLD Nq,Ib (MMX) (66h) !VPSRLD Hx,Ux,Ib (SSE2) |
PSRAD Nq,Ib (MMX) (66h) !VPSRAD Hx,Ux,Ib (SSE2) |
PSLLD Nq,Ib (MMX) (66h) !VPSLLD Hx,Ux,Ib (SSE2) |
|||||
| group #13 (MVEX 66h) (0Fh,72h) |
|
VPSRLD Hz {Kw}, Si32r (Wzt),Ib (W=0) (K1OM) |
VPSRAD Hz {Kw}, Si32r (Wzt),Ib (W=0) (K1OM) |
VPSLLD Hz {Kw}, Si32r (Wzt),Ib (W=0) (K1OM) |
|||||
| group #13 (EVEX 66h) (0Fh,72h) |
|
VPRORD Hn {K} {z}, B32 (Wn),Ib (W=0) VPRORQ Hn {K} {z}, B64 (Wn),Ib (W=1) (AVX512F,VL) |
VPROLD Hn {K} {z}, B32 (Wn),Ib (W=0) VPROLQ Hn {K} {z}, B64 (Wn),Ib (W=1) (AVX512F,VL) |
VPSRLD Hn {K} {z}, B32 (Wn),Ib (W=0) (AVX512F,VL) |
VPSRAD Hn {K} {z}, B32 (Wn),Ib (W=0) VPSRAQ Hn {K} {z}, B64 (Wn),Ib (W=1) (AVX512F,VL) |
VPSLLD Hn {K} {z}, B32 (Wn),Ib (W=0) (AVX512F,VL) |
|||
| group #14 (0Fh,73h) |
|
PSRLQ Nq,Ib (MMX) (66h) !VPSRLQ Hx,Ux,Ib (SSE2) |
(66h) !VPSRLDQ Hx,Ux,Ib (SSE2) |
PSLLQ Nq,Ib (MMX) (66h) !VPSLLQ Hx,Ux,Ib (SSE2) |
(66h) !VPSLLDQ Hx,Ux,Ib (SSE2) |
||||
| group #14 (EVEX 66h) (0Fh,73h) |
|
VPSRLQ Hn {K} {z}, B64 (Wn),Ib (W=1) (AVX512F,VL) |
VPSRLDQ Hn, Wn,Ib (W=x) (AVX512BW,VL) |
VPSLLQ Hn {K} {z}, B64 (Wn),Ib (W=1) (AVX512F,VL) |
VPSLLDQ Hn, Wn,Ib (W=x) (AVX512BW,VL) |
||||
| group #15 (0Fh,AEh) |
|
FXSAVE M (see CPUID) |
FXRSTOR M (see CPUID) |
VLDMXCSR Md (SSE) |
VSTMXCSR Md (SSE) |
APX! XSAVE M (n/a) (see CPUID) PTWRITE My (F3h) (see CPUID) |
APX! XRSTOR M (n/a) (see CPUID) |
APX! XSAVEOPT M (n/a) (see CPUID) CLWB M (66h) (see CPUID) CLRSSBSY Mq (F3h) (see CPUID) |
CLFLUSH M (n/a) (see CPUID) CLFLUSHOPT M (66h) (see CPUID) |
| |
RDFSBASE Ry (F3h) (see CPUID) |
RDGSBASE Ry (F3h) (see CPUID) |
WRFSBASE Ry (F3h) (see CPUID) |
WRGSBASE Ry (F3h) (see CPUID) |
PTWRITE Ry (F3h) (see CPUID) |
LFENCE#r/m (n/a) (SSE2-MEM) INCSSP Ry (F3h) (see CPUID) |
MFENCE#r/m (n/a) (SSE2-MEM) TPAUSE Ry ... (66h) (see CPUID) UMONITOR Rv (F3h) (see CPUID) UMWAIT Ry ... (F2h) (see CPUID) |
SFENCE#r/m (n/a) (SSE-MEM) PCOMMIT (F8h) (66h) (see CPUID) |
|
| group #15 (VEX F2h) (0Fh,AEh) |
|
SPFLT Ry (K1OM) |
CLEVICT0 M (K1OM) |
||||||
| group #15 (MVEX F2h) (0Fh,AEh) |
|
CLEVICT0 M (K1OM) |
|||||||
| group #15 (VEX F3h) (0Fh,AEh) |
|
DELAY Ry (K1OM) |
CLEVICT1 M (K1OM) |
||||||
| group #15 (MVEX F3h) (0Fh,AEh) |
|
CLEVICT1 M (K1OM) |
|||||||
| group #16 (0Fh,18h) |
|
PREFETCHNTA M (SSE-MEM) HINT_NOP R[bv] (P6+) |
PREFETCHT0 M (SSE-MEM) HINT_NOP R[bv] (P6+) |
PREFETCHT1 M (SSE-MEM) HINT_NOP R[bv] (P6+) |
PREFETCHT2 M (SSE-MEM) HINT_NOP R[bv] (P6+) |
PREFETCHRST2 M (MOVRS) HINT_NOP R[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
PREFETCHIT1 M.rIP (PREFETCHI) HINT_NOP R[bv] (P6+) |
PREFETCHIT0 M.rIP (PREFETCHI) HINT_NOP R[bv] (P6+) |
| group #16 (VEX) (0Fh,18h) |
|
VPREFETCHNTA M (K1OM) |
VPREFETCHT0 M (K1OM) |
VPREFETCHT1 M (K1OM) |
VPREFETCHT2 M (K1OM) |
VPREFETCHENTA M (K1OM) |
VPREFETCHET0 M (K1OM) |
VPREFETCHET1 M (K1OM) |
VPREFETCHET2 M (K1OM) |
| group #16 (MVEX) (0Fh,18h) |
|
VPREFETCHNTA M (K1OM) |
VPREFETCHT0 M (K1OM) |
VPREFETCHT1 M (K1OM) |
VPREFETCHT2 M (K1OM) |
VPREFETCHENTA M (K1OM) |
VPREFETCHET0 M (K1OM) |
VPREFETCHET1 M (K1OM) |
VPREFETCHET2 M (K1OM) |
| group #16 (0Fh,19h) |
|
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
| group #16 (0Fh,1Ah) |
|
(n/a) BNDLDX rB,M.ib (MPX) (66h) BNDMOV rB,mB/M (MPX) (F3h) BNDCL rB,Ey (MPX) (F2h) BNDCU rB,Ey (MPX) |
|||||||
| group #16 (0Fh,1Bh) |
|
(n/a) BNDSTX M.ib,rB (MPX) (66h) BNDMOV mB/M,rB (MPX) (F3h) BNDMK rB,My (MPX) (F2h) BNDCN rB,Ey (MPX) |
|||||||
| group #16 (0Fh,1Ch) |
|
CLDEMOTE M (see CPUID) HINT_NOP R[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
| group #16 (0Fh,1Dh) |
|
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
| group #16 (0Fh,1Eh) |
|
HINT_NOP E[bv] (P6+) |
(F3h) RDSSPD Rd RDSSPQ Rq (see CPUID) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
(F3h) ENDBR64 (FAh) ENDBR32 (FBh) (see CPUID) |
| group #16 (0Fh,1Fh) |
|
NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
HINT_NOP E[bv] (P6+) |
| group #17 (VEX) (0F 38 F3) |
|
BLSRv By,Ey (BMI) |
BLSMSKv By,Ey (BMI) |
BLSIv By,Ey (BMI) |
|||||
| group #17 (EVEX NP) (0F 38 F3) |
|
{NF} BLSR By,Ey (BMI,APX) |
{NF} BLSMSK By,Ey (BMI,APX) |
{NF} BLSI By,Ey (BMI,APX) |
|||||
| group #18 (MVEX 66) (0F 38 C6) |
|
VGATHER- PF0HINTDPS Uf32 (Mdt.z) {Kw.!0} (W=0) VGATHER- PF0HINTDPD Uf64 (Mqt.z.y) {Kw.!0} (1) (K1OM,VSIB) |
VGATHER- PF0DPS Uf32 (Mdt.z) {Kw.!0} (W=0) (K1OM,VSIB) |
VGATHER- PF1DPS Uf32 (Mdt.z) {Kw.!0} (W=0) (K1OM,VSIB) |
VSCATTER- PF0HINTDPS Uf32 (Mdt.z) {Kw.!0} (W=0) VSCATTER- PF0HINTDPD Uf64 (Mqt.z.y) {Kw.!0} (1) (K1OM,VSIB) |
VSCATTER- PF0DPS Uf32 (Mdt.z) {Kw.!0} (W=0) (K1OM,VSIB) |
VSCATTER- PF1DPS Uf32 (Mdt.z) {Kw.!0} (W=0) (K1OM,VSIB) |
||
| group #18 (EVEX 66) (0F 38 C6) |
|
VGATHER- PF0DPS Md.n {K.!0} (W=0) VGATHER- PF0DPD Mq.h {K.!0} (W=1) (A`PF,VL,VSIB) |
VGATHER- PF1DPS Md.n {K.!0} (W=0) VGATHER- PF1DPD Mq.h {K.!0} (W=1) (A`PF,VL,VSIB) |
VSCATTER- PF0DPS Md.n {K.!0} (W=0) VSCATTER- PF0DPD Mq.h {K.!0} (W=1) (A`PF,VL,VSIB) |
VSCATTER- PF1DPS Md.n {K.!0} (W=0) VSCATTER- PF1DPD Mq.h {K.!0} (W=1) (A`PF,VL,VSIB) |
||||
| group #18 (EVEX 66) (0F 38 C7) |
|
VGATHER- PF0QPS Md.n {K.!0} (W=0) VGATHER- PF0QPD Mq.n {K.!0} (W=1) (A`PF,VL,VSIB) |
VGATHER- PF1QPS Md.n {K.!0} (W=0) VGATHER- PF1QPD Mq.n {K.!0} (W=1) (A`PF,VL,VSIB) |
VSCATTER- PF0QPS Md.n {K.!0} (W=0) VSCATTER- PF0QPD Mq.n {K.!0} (W=1) (A`PF,VL,VSIB) |
VSCATTER- PF1QPS Md.n {K.!0} (W=0) VSCATTER- PF1QPD Mq.n {K.!0} (W=1) (A`PF,VL,VSIB) |
||||
| group #19 (F3) (0F 38 D8) |
|
AESENCWIDE- 128KL M (KL) |
AESDECWIDE- 128KL M (KL) |
AESENCWIDE- 256KL M (KL) |
AESDECWIDE- 256KL M (KL) |
||||
On 8086/8088 processors the following behavior was supported instead.
| mod R/M |
|
xx000xxx | xx001xxx | xx010xxx | xx011xxx | xx100xxx | xx101xxx | xx110xxx | xx111xxx |
| ... | ... | ||||||||
| group #2 (D0h) |
|
ROL Eb,1 | ROR Eb,1 | RCL Eb,1 | RCR Eb,1 | SHL Eb,1 | SHR Eb,1 | OR Eb,-1(,1) |
SAR Eb,1 |
| group #2 (D1h) |
|
ROL Ew,1 | ROR Ew,1 | RCL Ew,1 | RCR Ew,1 | SHL Ew,1 | SHR Ew,1 | OR Ew,-1(,1) | SAR Ew,1 |
| group #2 (D2h) |
|
ROL Eb,CL | ROR Eb,CL | RCL Eb,CL | RCR Eb,CL | SHL Eb,CL | SHR Eb,CL | OR Eb,-1(,CL) | SAR Eb,CL |
| group #2 (D3h) |
|
ROL Ew,CL | ROR Ew,CL | RCL Ew,CL | RCR Ew,CL | SHL Ew,CL | SHR Ew,CL | OR Ew,-1(,CL) | SAR Ew,CL |
| ... | ... | ||||||||
| group #1A (8Fh) |
|
POP Ew | ??? | ??? | ??? | ??? | ??? | ??? | ??? |
| ... | ... | ||||||||
| group #4 (FEh) |
|
INC Eb | DEC Eb | CALL Eb | CALL Mp (w:w)b |
JMP Eb | JMP Mp (w:w)b |
PUSH Eb | PUSH* Eb |
| CALL (IND:TMP)b |
JMP (IND:TMP)b |
||||||||
| group #5 (FFh) |
|
INC Ew | DEC Ew | CALL Ew | CALL Mp (w:w) |
JMP Ew | JMP Mp (w:w) |
PUSH Ew | PUSH* Ew |
| CALL (IND:TMP) |
JMP (IND:TMP) |
||||||||
| ... | ... | ||||||||
| group #11 (C6h) |
|
MOV Eb,Ib | ??? | ??? | ??? | ??? | ??? | ??? | ??? |
| group #11 (C7h) |
|
MOV Ew,Iw | ??? | ??? | ??? | ??? | ??? | ??? | ??? |
| ... | ... | ||||||||
note: The opcodes marked with * are aliases to other opcodes.
© 1996-2024 by Christian Ludloff. All rights reserved. Use at your own risk.