x86 architecture
3DNow! opcodes


note: AMD abandoned 3DNow! as well as enhanced 3DNow! with their Family 15h processors, and only supports PREFETCHx now

The PREFETCHx instruction is using the reg field of the mod R/M byte to determine the desired prefetch type (x).

 
0Fh xxh
 		 xDh xEh xFh
 
0xh
 		 PREFETCHx
M		 FEMMS refer to
table
below
 
opcode PREFETCHx instruction
0Fh,0Dh,xx000xxxb PREFETCH line into E state
0Fh,0Dh,xx001xxxb PREFETCHW line into M state
0Fh,0Dh,xx002xxxb PREFETCHWT1 line with intent to
write (E state), and T1 locality (L2)
(see CPUID for PREFETCHWT1 flag)
0Fh,0Dh,xx003xxxb reserved, alias to PREFETCH
0Fh,0Dh,xx004xxxb reserved, alias to PREFETCH
0Fh,0Dh,xx005xxxb reserved, alias to PREFETCH
0Fh,0Dh,xx006xxxb reserved, alias to PREFETCH
0Fh,0Dh,xx007xxxb reserved, alias to PREFETCH


The 3DNow! instruction encoding differs from the regular instruction encoding, in that the mod R/M (and SIB) byte as well as an optional displacement follow directly after the two 0Fh prefix bytes. The byte selecting the instruction itself is appended as the last byte.


0Fh 0Fh
... xxh		  
x0h
 		 x1h x2h x3h x4h x5h x6h x7h
 
0xh
 		 TFADDS.Rx
TFd,TFs1,TFs2
(TFP)		 TFADDD.Rx
TFd,TFs1,TFs2
(TFP)		 TFSUBS.Rx
TFd,TFs1,TFs2
(TFP)		 TFSUBD.Rx
TFd,TFs1,TFs2
(TFP)		 TFMULS.Rx
TFd,TFs1,TFs2
(TFP)		 TFMULD.Rx
TFd,TFs1,TFs2
(TFP)		 TFDIVS.Rx
TFd,TFs1,TFs2
(TFP)		 TFDIVD.Rx
TFd,TFs1,TFs2
(TFP)
 
1xh
 		 TFSQRTS.Rx
TFd,TFs
(TFP)		 TFSQRTD.Rx
TFd,TFs
(TFP)		 TFPREMS
TFd,TFs1,TFs2
(TFP)		 TFPREMD
TFd,TFs1,TFs2
(TFP)		 TFCOMI
TFd,TFs
(TFP)		 TFUCOMI
TFd,TFs
(TFP)
 
2xh
 		 TFCMOVB
TFd,TFs
(TFP)		 TFCMOVE
TFd,TFs
(TFP)		 TFCMOVBE
TFd,TFs
(TFP)		 TFCMOVU
TFd,TFs
(TFP)		 TFCMOVNB
TFd,TFs
(TFP)		 TFCMOVNE
TFd,TFs
(TFP)		 TFCMOVNBE
TFd,TFs
(TFP)		 TFCMOVNU
TFd,TFs
(TFP)
 
3xh
 		 TFABS
TFd,TFs
(TFP)		 TFCPYS
TFd,TFs1,TFs2
(TFP)		 TFCPYSN
TFd,TFs1,TFs2
(TFP)		 TFCPYSE
TFd,TFs1,TFs2
(TFP)
 
4xh
 		 TFCVT32D.Rx
TFd,TFs
(TFP)		 TFCVT32S.Rx
TFd,TFs
(TFP)		 TFCVT64D.Rx
TFd,TFs
(TFP)		 TFCVT64S.Rx
TFd,TFs
(TFP)		 TFCVTF64.Rx
TFd,TFs
(TFP)		 TFCVTF32.Rx
TFd,TFs
(TFP)		 TFCVTDS.Rx
TFd,TFs
(TFP)
 
5xh
 		 TFLD32
TF0...7,Md
(TFP)		 TFLD32
TF8...15,Md
(TFP)		 TFLD64
TF0...7,Mq
(TFP)		 TFLD64
TF8...15,Mq
(TFP)		 TFST32
Md,TF0...7
(TFP)		 TFST32
Md,TF8...15
(TFP)		 TFST64
Mq,TF0...7
(TFP)		 TFST64
Mq,TF8...15
(TFP)
 
6xh
 
 
7xh
 
 
8xh
 		 PFRCPV
Pq,Qq
(Geode LX)		 PFRSQRTV
Pq,Qq
(Geode LX)
 
9xh
 		 PFCMPGE
Pq,Qq		 PFMIN
Pq,Qq		 PFRCP
Pq,Qq		 PFRSQRT
Pq,Qq
 
Axh
 		 PFCMPGT
Pq,Qq		 PFMAX
Pq,Qq		 PFRCPIT1
Pq,Qq		 PFRSQIT1
Pq,Qq
 
Bxh
 		 PFCMPEQ
Pq,Qq		 PFMUL
Pq,Qq		 PFRCPIT2
Pq,Qq		 PMULHRW
Pq,Qq
 
Cxh
 
 
Dxh
 
 
Exh
 
 
Fxh
 

0Fh 0Fh
... xxh		  
x8h
 		 x9h xAh xBh xCh xDh xEh xFh
 
0xh
 		 PI2FW*
Pq,Qq		 PI2FD
Pq,Qq
 
1xh
 		 PF2IW*
Pq,Qq		 PF2ID
Pq,Qq
 
2xh
 
 
3xh
 
 
4xh
 
 
5xh
 
 
6xh
 
 
7xh
 
 
8xh
 		 PFNACC*
Pq,Qq		 PFPNACC*
Pq,Qq
 
9xh
 		 PFSUB
Pq,Qq		 PFADD
Pq,Qq
 
Axh
 		 PFSUBR
Pq,Qq		 PFACC
Pq,Qq
 
Bxh
 		 PSWAPD*
Pq,Qq		 PAVGUSB
Pq,Qq
 
Cxh
 
 
Dxh
 
 
Exh
 
 
Fxh
 


note: The opcodes marked with * are enhanced 3DNow! opcodes.

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