x86 architecture
task state segment




 
16-bit TSS
 
offset 1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
+00h LINK
+02h SP0
+04h SS0
+06h SP1
+08h SS1
+0Ah SP2
+0Ch SS2
+0Eh IP
+10h FLAGS
+12h AX
+14h CX
+16h DX
+18h BX
+1Ah SP
+1Ch BP
+1Eh SI
+20h DI
+22h ES
+24h CS
+26h SS
+28h DS
+2Ah LDTR
note White fields are dynamic, gray fields are static.

 
32-bit TSS
 
offset 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
+00h reserved LINK
+04h ESP0
+08h reserved SS0
+0Ch ESP1
+10h reserved SS1
+14h ESP2
+18h reserved SS2
+1Ch CR3
+20h EIP
+24h EFLAGS
+28h EAX
+2Ch ECX
+30h EDX
+34h EBX
+38h ESP
+3Ch EBP
+40h ESI
+44h EDI
+48h reserved ES
+4Ch reserved CS
+50h reserved SS
+54h reserved DS
+58h reserved FS
+5Ch reserved GS
+60h reserved LDTR
+64h IOPB offset reserved T
+68h SSP (if CET is supported)
+6Ch  
optional operating system data
 
+IOPB
offset
-32
 
optional interrupt redirection bitmap
 
+IOPB
offset
 
optional I/O permission bitmap
 
  x x x x x 1 1 1
note White fields are dynamic, gray fields are static.

 
64-bit TSS
 
offset 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
+00h reserved reserved
+04h RSP0
+08h
+0Ch RSP1
+10h
+14h RSP2
+18h
+1Ch reserved
+20h reserved
+24h IST_RSP1
+28h
+2Ch IST_RSP2
+30h
+34h IST_RSP3
+38h
+3Ch IST_RSP4
+40h
+44h IST_RSP5
+48h
+4Ch IST_RSP6
+50h
+54h IST_RSP7
+58h
+5Ch reserved reserved
+60h reserved reserved
+64h IOPB offset reserved T
+68h  
optional operating system data
 
+IOPB
offset
 
optional I/O permission bitmap
 
  x x x x x 1 1 1



 
task linking/nested tasks
 
task? nested top-level nested high nested low currently active
state? TSS #A TSS #B TSS #C TSS #D
TSS.descr(#A).B=1
TSS.EFLAGS.NT=0
TSS.LINK=ignored
TSS.descr(#B).B=1
TSS.EFLAGS.NT=1
TSS.LINK=TSS #A
TSS.descr(#C).B=1
TSS.EFLAGS.NT=1
TSS.LINK=TSS #B
TSS.descr(#D).B=1
EFLAGS.NT=1
TR=TSS #C



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© 1996-2024 by Christian Ludloff. All rights reserved. Use at your own risk.