x86 architecture
processor mode


 
processor mode
 
name EFER.LMA CR0.PE RFLAGS.VM CS.ar.L CS.ar.D CR4.VME TSS32.IRB[n] paging?
RM16 0 #1 0 n/a n/a 0 n/a n/a no
RM32 1
VM16 1 1 0 0 n/a optional
VM16E0 1 0
VM16E1 1
PM16 1 0 0 n/a n/a optional
PM32 1
CM16 1 #2 1 n/a 0 0 n/a n/a PAE is
required
CM32 0 1
PM64 1 0
notes descriptions
#1 This is known as legacy mode.
#2 This is known as long mode (LM).

 
processor paging
 
name EFER.LMA CR0.PG CR4.PAE CR4.PSE PDE.PS page size table levels modes
NONE 0 0 n/a n/a n/a n/a n/a RM, VM, PM
4K 1 0 0 n/a 4 KB 2 VM or PM
PSE_4K 1 0 1 0 4 KB 2
PSE_4M 1 4 MB
PAE_4K 1 1 n/a 0 4 KB 3
PAE_2M 1 2 MB
name EFER.LMA CR0.PG CR4.PAE CR4.VA57 PDE.PS page size table levels modes
PAE_4K 1 1 #1 1 #1 0 #1 PML3E.PS=0
PML2E.PS=0		 4 KB 4 CM or PM64
PAE_2M PML3E.PS=0
PML2E.PS=1		 2 MB
PAE_1G PML3E.PS=1
PML2E.PS=x		 1 GB
PG5_4K 1 #1 PML5E.PS=0
PML4E.PS=0
PML3E.PS=0
PML2E.PS=0		 4 KB 5
PG5_2M PML5E.PS=0
PML4E.PS=0
PML3E.PS=0
PML2E.PS=1		 2 MB
PG5_1G PML5E.PS=0
PML4E.PS=0
PML3E.PS=1
PML2E.PS=x		 1 GB
PG5_HT
(half tera)		 PML5E.PS=0
PML4E.PS=1
PML3E.PS=x
PML2E.PS=x		 512 GB
PG5_QP
(quarter peta)		 PML5E.PS=1
PML4E.PS=x
PML3E.PS=x
PML2E.PS=x		 256 TB
notes descriptions
#1 The following consistency checks apply:

bit transition check
CR0.PG from 0 to 1 if ((EFER.LME=1) & ((CR4.PAE=0) | (CS.ar.L=1))) then #GP(0)
EFER.LME changes if (CR0.PG=1) then #GP(0)
CR4.PAE from 1 to 0 if (EFER.LMA=1) then #GP(0)
CR4.VA57 changes if (EFER.LMA=1) then #GP(0)
CR0.PG from 1 to 0 if (CR4.PCIDE=1) then #GP(0)
CR4.PCIDE from 0 to 1 if ((EFER.LMA=0) | (CR3.PCID<>0)) then #GP(0)
 

 
privilege level
 
name stored in values description
IOPL RFLAGS.IOPL 0...3 I/O privilege level
CPL SS.CPL or CPL 0...3 current privilege level
RPL selector.RPL 0...3 requestor privilege level
DPL descriptor.DPL 0...3 descriptor privilege level

 
address size
 
mode default 67h effective
Legacy Mode 16 no 16
yes 32
32 yes 16
no 32
Long
Mode		 CM 16 no 16
yes 32
32 yes 16
no 32
PM64 64 yes 32
no 64
 
 
operand size
 
mode default 66h REX.W=1 effective
Legacy Mode 16 no n/a 16
yes 32
32 yes 16
no 32
Long
Mode		 CM 16 no n/a 16
yes 32
32 yes 16
no 32
PM64 32 yes no 16
no 32
ignored yes 64
64 yes no 16
yes 64
no ignored 64
note The default operand size for PM64 is 32-bit except
for implicit stack referencesD64, near branchesDf64 --
see the 1 byte opcodes and 2 byte opcodes -- and
accesses to the CRx/DRx or GDT/IDT registersF64.


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