segment registers
| CS, SS, DS, ES, FS, GS |
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| 1 5 |
1 4 |
1 3 |
1 2 |
1 1 |
1 0 |
9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | internal descriptor cache | |||
| CS for a segment or a selector | 32-bit base |
32-bit limit | access rights |
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| SS for a segment or a selector | 32-bit base |
32-bit limit | access rights |
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| DS for a segment or a selector | 32-bit base |
32-bit limit | access rights |
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| ES for a segment or a selector | 32-bit base |
32-bit limit | access rights |
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| FS for a segment or a selector | 32-bit base | 32-bit limit | access rights |
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| 64-bit base #1 | |||||||||||||||||||
| GS for a segment or a selector | 32-bit base | 32-bit limit | access rights |
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| 64-bit base #1 | |||||||||||||||||||
| note | description | ||||||||||||||||||
| #1 | The upper 32 bits can be set to non-zero values through MSRs. | ||||||||||||||||||
© 1996-2025 by Christian Ludloff. All rights reserved. Use at your own risk.