x86 architecture
descriptors


 
available descriptor (P=0)
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
+4  
available
 		 0 DPL S TYPE available
+0  
available
 

 
code (application) segment descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
+4 BASE (bits 31...24) G D  r.  A
V
L		 LIMIT
(bits 19...16)		 P DPL S
=
1		 X
=
1		 C R A BASE (bits 23...16)
 L 
+0  
BASE (bits 15...0)
 		 LIMIT (bits 15...0)

 
data (application) segment descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
+4 BASE (bits 31...24) G B r. A
V
L		 LIMIT
(bits 19...16)		 P DPL S
=
1		 X
=
0		 E W A BASE (bits 23...16)
+0  
BASE (bits 15...0)
 		 LIMIT (bits 15...0)

 
LDT (system segment) descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
+12
 		 reserved 0 0 0 0 0 reserved
 
+8
 		 BASE (bits 63...32)
+4  
BASE (bits 31...24)
 		 G r. r. A
V
L		 LIMIT
(bits 19...16)		 P DPL S
=
0		 0 G
=
0		 1 0 BASE (bits 23...16)
+0  
BASE (bits 15...0)
 		 LIMIT (bits 15...0)

 
TSS (system segment) descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
+12
 		 reserved 0 0 0 0 0 reserved
 
+8
 		 BASE (bits 63...32)
+4  
BASE (bits 31...24)
 		 G r. r. A
V
L		 LIMIT
(bits 19...16)		 P DPL S
=
0		  D  G
=
0		 B V
=
1		 BASE (bits 23...16)
 1 
+0  
BASE (bits 15...0)
 		 LIMIT (bits 15...0)
note Since the TR.ar.V bit is set to 0 during a processor RESET or INIT, it should act like a valid bit, and cause a #TS(0) exception on all implicit TSS accesses (stack switch, task switch, TSS32.IOPB, or TSS32.IRB). Most processors don't implement that behavior though.

 
call gate descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
+12
 		 reserved 0 0 0 0 0 reserved
 
+8
 		 OFFSET (bits 63...32)
+4 OFFSET (bits 31...16) P DPL S
=
0		  D  G
=
1		 00 res. PARAM COUNT
(0...31)
 1  reserved
 
+0
 		  CS selector  OFFSET (bits 15...0)
 PM64 CS selector 

 
task gate descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
+4  
reserved
 		 P DPL S
=
0		 0 G
=
1		 01 reserved
+0  
TSS selector
 		 reserved

 
interrupt gate descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
+12
 		 reserved
 
+8
 		 OFFSET (bits 63...32)
+4  
OFFSET (bits 31...16)
 		 P DPL S
=
0		  D  G
=
1		 10 reserved
 1  reserved IST
 
+0
 		  CS selector  OFFSET (bits 15...0)
 PM64 CS selector 

 
trap gate descriptor
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
 
+12
 		 reserved
 
+8
 		 OFFSET (bits 63...32)
+4  
OFFSET (bits 31...16)
 		 P DPL S
=
0		  D  G
=
1		 11 reserved
 1  reserved IST
 
+0
 		  CS selector  OFFSET (bits 15...0)
 PM64 CS selector 

 
NULL descriptor (suggested layout for traditional LGDT use)
 
offset 3
1		 3
0		 2
9		 2
8		 2
7		 2
6		 2
5		 2
4		 2
3		 2
2		 2
1		 2
0		 1
9		 1
8		 1
7		 1
6		 1
5		 1
4		 1
3		 1
2		 1
1		 1
0		 9 8 7 6 5 4 3 2 1 0
+4  
reserved
 		 GDT base (bits 31...16)
+0  
GDT base (bits 15...0)
 		 GDT limit (bits 15...0)


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© 1996-2024 by Christian Ludloff. All rights reserved. Use at your own risk.